f76feb85-1525-4c68-8761-084dbcdb2a3720221027094053600naun:naunmdt@crossref.orgMDT DepositInternational Journal of Communications1998-448010.46300/9107http://www.naun.org/cms.action?id=30333520223520221610.46300/9107.2022.16https://npublications.com/journals/communications/2022.phpRajuHajareDepartment of Electronics and Telecommunication Engineering, BMS Institute of Technology and Management, Yelahanka, Bangalore-64, Karnataka, IndiaThe VLSI Technology has been progressing significantly and the circuits which consume less power become major concern factor for designing todays ICs for Microprocessors and other various systems components. The Datapath is important part of a system. Adders, multipliers, and shift registers are the major components of data path unit of ALU. Almost all digital circuits and chips are made of MOSFET as the basic switching element. But same MOSFET suffers due to Short Channel Effects (SCEs) when scaled down to nano regime, which has promoted multigate device called FinFET. And this FinFET device overcomes the SCEs at technology nodes. In this paper 28T and 16T MOSFET and FinFET based full adders are designed. Using adders, 4x4 array multiplier is designed using both MOSFET and FinFET technology along with it Serial in Serial out shift register designs. The circuits designed based on MOSFET and FinFET are analyzed in terms of power and delay at various nodes. From the software characterization and analysis, it is understood that FinFET based circuits promise better performance at lower technology nodes like 22nm and 14nm than higher technology nodes in MOSFET like 250nm, 180nm, 90nm and 45nm. Hence FinFET becomes a promising device for future IC technology.102720221027202254609https://npublications.com/journals/communications/2022/a182006-009(2022).pdf10.46300/9107.2022.16.9https://npublications.com/journals/communications/2022/a182006-009(2022).pdf10.1109/5.915374D. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, Y. Taur and H.-S. P. Wong, "Device scaling limits of Si MOSFETs and their application dependencies," Proc. of the IEEE, vol. 89, no. 3, pp. 259-288, Mar. 2001. 10.1109/16.887014FinFET—A Self-Aligned Double-Gate MOSFET Scalable to 20 nm DighHisamoto, Member, IEEE, Wen-Chin Lee, Jakub Kedzierski, Hideki Takeuchi, KazuAsano, Member, IEEE, Charles Kuo , Erik Anderson, Ts u-Jae King, Jeffrey Bokor, Fellow, IEEE, and Chenming Hu, Fellow, IEEE (2000).. T.-C. Chen, "Overcoming research challenges for CMOS scaling: Industry directions," in Proc. Int. Conf. on Solid-State and IC Technology, pp. 4-7, Oct. 2006. "International Technology Roadmap for Semiconductors,"[Online]. vailable: 10.1007/s00542-015-2468-9Raju Hajare, C. Lakshminarayana,” Performance enhancement of FinFET and CNTFET at different node technologies ”Springer, Microsystem technologies, March-2015. 10.1007/978-0-387-71752-4_1J.-P. Colinge, "The SOI MOSFET: From single gate to multigate," in FinFETs and Other Multi-Gate Transistors, 1st ed., J.-P. Colinge, Ed., New York, Springer, 2008, pp. 1-48. 10.1109/tvlsi.2002.808433D. E. Duarte, N. Vijaykrishnan and M. J. Irwin, "A clock power model to evaluate impact of architectural and technology optimizations," IEEE Trans. VLSI Systems, vol. 10, no. 6, pp. 844-855, Dec. 2002 10.1109/isqed.2006.91W. Zhao and Y. Cao, "New generation of predictive technology model for sub-45nm design exploration," in Proc. Int. Symp. Quality of Electronic Design, pp. 585-590, May 2006, 10.1007/978-0-387-71752-4_3M.V.Dunga, C.-H. Lin, A. M. Niknejad and C. Hu, "BSIM-CMG: A compact model for multi-gate transistors," in FinFETs and Other Multi-Gate Transistors,1st ed.,J.-P. Coligne, Ed., New York, Springer, 2008, pp. 113-153. 10.1109/mdt.2010.39Darsen D. Lu, Chung-Hsun Lin, Ali M. Niknejad and Chenming Hu "Compact Modeling of Variation in FinFET SRAM Cells" IEEE Design and Test of Computers 2010. Nirmal, Vijayakumar and Sam Jabaraj (2010), Nand Gate using FINFET for Nano-Scale Technology, In International Journal of Engineering Science and Technology, Vol. 2(5), pp-1351-1358. 10.1109/uksim.2011.108Christiensen D.C. Arandilla, Anastacia B. Alvarez, and Christian Raymund K. Roque “Static Noise Margin of 6T SRAM Cell in 90-nm CMOS” IEEE UKSim 13th International Conference on Modelling and Simulation, pp534-539, 2011. Cyril Prasannraj. Likitha,” Performance comparison of CMOS and FINFET based SRAM for 22nm Technology” International Journal of Conceptions on Electronics and Communication Engineering Vol. 1, Issue. 1, Dec’ 2013 10.1109/mcas.2011.942068Balwinder Raj, A.K Saxena and S. Dasgupta, “NanoscaleFinFET based SRAM cell design: Analysis of Performance metric, Process variation, Underlapped FinFET and temperature effect”, IEEE circuits and systems magazine, 2010. Ajay Nuggehallibhoj, “Device-Circuit Co-Design Approaches for MultiGate FET Technologies”, Princeton University, 2013. 10.1109/mdt.2010.39Darsen D. Lu , Chung-Hsun Lin, Ali M. Niknejad and Chenming Hu, “Compact Modelling of variation in FinFET SRAM Cells”, University of California, Berkeley.IEEE Design and test of Computers, June 2014. Alexei Nazarow, J. P. Colinge et al (2011). Semiconductor-On- Insulator Material for Nanoelectronics Applications, Springer Heidelberg Dordrecht, London. 10.1017/cbo9781139343466Jerry G. Fossem, Vishal P. Trivedi, “Ultra-Thin-Body MOSFETs and FinFETs”, Cambridge University Press, 2013. 10.1109/erect.2015.7498998Raju Hajare, et al,’ “Performance Evaluation of FinFET and nanowire at Different technology nodes”, International Conference on Emerging Research in Electronics, Computer Science and Technology, PP 114-119, 2015 10.1109/icetet.2011.23Deepa Yagain, Ankit Parakh, AkritiKedia ,Gunjankumar Gupta “Design and implementation of High speed, Low area Multiportedloadless 4T Memory Cell” IEEE Fourth International Conference on Emerging Trends in Engineering & Technology, 2011. 10.1017/cbo9781316156148.003Debajit Bhattacharya and Niraj K. Jha “FinFETs: From Devices to Architectures Princeton University, Princeton, NJ08544,USA, September 2014. 10.11591/ijres.v8.i1.pp51-60Raju Hajare et al,” Design and Software characterization of FinFET based full adders”, International Journal of Reconfigurable and Embedded Systems, Vol. 8, No. 1, pp. 51~60, March 2019 10.35940/ijeat.f8904.109119Raju Hajare et al,” Design and Performance Improvement of CNTFET Based Content Addressable Memory (CAM) Cells”, International Journal of Engineering and Advanced Technology (IJEAT) ISSN: 2249 – 8958, Volume9 Issue-1, October 2019.